Written by Christoph Schildknecht¹, Daniel Riegger¹, Simon Gross¹, and David Brunner^1
1Skope MRT

Modern MRI systems use many RF receive channels and additional sensor channels to improve imaging. To avoid costly and bulky cabling to the outside of the Faraday cage, the signal digitation is desirably done at the magnet. However, doing so poses a significant challenge given the strict power and noise emission constraints.

To address this challenge, a new lean RF receiver architecture is presented here. This architecture digitizes RF signals at the magnet and transports the data directly from the analogue-to-digital converter optically via JESD204B subclass 1 to a backend outside the Faraday cage. This enables low-power, high-fidelity digitization of the RF signals with low phase noise and precise synchronisation of the measurement to external triggers while circumventing many technical difficulties.

Introduction

Modern MRI systems utilize increasingly many RF receive channels to enhance imaging capabilities. For MR receivers, even 128-channel systems have been developed [1-5]. Additional sensors deployed in the magnet, such as motion trackers or field probes [6-7] increase the number of signals that need to be routed out further. Analog signal routing becomes consequently bulky, lossy and costly. Furthermore, all connections need to be fed through the Faraday cage, which is a particular challenge for add-on systems. Modern MR systems therefore deploy digitization typically at or in the magnet and transport the data out by fiber optics [5,8-10].
However, electronics placed in this environment faces fierce noise emission and power constraints. Particularly, implementing high-speed computational units such as FGPAs can be challenging. In this work, we present an RF receiver architecture that digitizes the RF signals at the magnet and transports the data directly via JESD204B [11] over fiber [12-13] optically to the outside where further processing is performed. This architecture significantly reduces the technical difficulty in implementing the receiver. The approach is demonstrated to enable low-power, high fidelity RF digitization, low phase noise and jitter while offering deterministic latency in asynchronous operation using the JESD204B subclass 1 interface.

Methods

Thee receiver architecture is shown in Figs. 1 and 2. The system is composed of two parts: The RF head inside and the digital backend outside of the Faraday cage. The RF head contains the 16-channel analog RF frontend.Signals are digitized and optionally pre-processed by a 16-channel analog-to-digital converter (ADC) with a JESD204B subclass 1 interface. Since the output of the ADC chip is directly connected to the electro-optical converters no further processing hardware such as an FPGA is required in the RF head [12-13]. To achieve constant latency, the JESD interface is resynchronized for each acquisition. In the RF head, the clocks are generated from an optically connected reference with a loop-bandwidth higher than the signal bandwidth rendering it immune against vibration or gradient induced phase noise disturbances as seen elsewhere [14]. Inside the digital backend, an FPGA receives the JESD204B and processes it to the desired format. The processed data and additional meta-data are then streamed over ethernet to clients by a system-on-module. The digital backend also features a trigger and reference clock I/O. Synchronization accuracy to an asynchronous external trigger is determined by measuring the envelope falling edge of a block pulse. This measurement is done with two different systems to verify that the latency is constant across hardware. System phase noise performance is determined by acquiring a 298MHz test signal from a signal generator (SMB100B-B1H) and integrated in the 10Hz to 100kHz band. The phase noise for clock transmission of the optical transceiver is measured with a VNA measuring the phase noise with a loopback test with one transceiver inside a 3T magnet.

Figure 1: Overview of the system architecture. The RF head located next to the scanner in the Faraday cage is connected to the digital backend in the technical room solely with one multi-fiber optical cable.

Figure 2: Schematic overview. The RF head consists of 16 independent RF gain stages and down-converters. The ADC converts and decimates all 16 channels synchronously before outputting the data via the JESD204B protocol to the optical converter module (SFP+). The clocking of the head is provided by a PLL. The clock transmission via optical module was not found to require cleaning by a local oscillator. A microcontroller (MCU) is employed for configuring the units and communicating to the backend.

Results

The measured synchronization accuracy (Fig. 3) is better than +-10ns. The synchronization accuracy is mainly bound by the internal sampling rate of the asynchronous external trigger. The roundtrip phase noise of the optical transmission alone was around 50fs for a bandwidth of 100kHz as shown in Fig. 4. The overall phase noise of a test signal acquired with the full system is shown in Fig. 5. The integrated phase noise in the 10Hz to 100kHz band was determined at 142fs.

Figure 3: Synchronization accuracy to an external asynchronous trigger measured on two different systems. In the top left the RAW RF samples are plotted on top of each other. On the top right its amplitude envelop is plotted for both devices as seen by the slightly different amplitude scaling. In the bottom left, the timing of the envelope midpoint crossing is shown. The bottom right shows a histogram of the synchronization variation exhibiting a 10ns accuracy window.

Figure 4: Jitter performance of the roundtrip (two-way) transmission of a 3GHz sinusoidal clock signal with transceiver inside the 3T bore. Single and multi-mode transceivers were tested with the direction of the magnetic field perpendicular or planar to the module. Additionally, a reference measurement with the transceiver outside the magnet and a reference where the fiber optics is replaced by a coaxial line are shown. It is expected that the phase noise for a one-way trip is half the presented values.

Figure 5: Phase noise of the entire system acquiring a 298MHz input signal. The jitter integrated from 10Hz to 100kHz is 142fs rms, which relates to a phase noise floor of 266urad at 7T and would permit an SNR in this range close to carrier of up to 79dB at 128MHz and 72dB at 298MHz according to [18].

Discussion and conclusion

The measured phase noise from the optical transmission was shown to not limit the system performance such that splitting the receiver into two parts did not impact the RF performance. The synchronization accuracy to an external asynchronous trigger of less than 10ns allows for precise temporal mapping of the measured gradient fields with NMR field probes which this receiver was designed for. If an external system runs synchronously to the receiver, even accuracies to the level of 0.5ps can be expected [15]. Furthermore, given its asynchronous operation (e.g. external trigger), more devices, such as the gradient and RF transmit chain, could be connected to the JESD204B subclass 1 interface of the FPGA providing tight synchronization and phase locking between the units. Optical and galvanic JESD204B interfaces could be combined enabling endpoints to be situated in different locations. With JESD204C [16] and JESD204D [17] even denser systems are possible. The system architecture with its clock generation and most of the digital part located outside of the Faraday cage has also shown benefits in the required RF shielding, power consumption and clocking robustness.

References

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